TF test results
Synced 12:21 UTC, 2 h ago

Data as of 29 Oct 2026, 12:21 UTC

Last LAVA sync
29 Oct 2026, 12:21 UTC
Last Jenkins sync
29 Oct 2026, 12:23 UTC
Last S3 export sync
7 Oct 2026, 09:53 UTC
Open fetch errors
6,510
About the data
  1. Boards
  2. STMicroelectronics
  3. STM32MP15X-Eval

STM32MP15X-Eval

STM32MP15X, STMicroelectronics. stm32mp15x-eval

Live First seen 1 Oct 2025, last seen 29 Oct 2026. 3 units live.

Evaluations

256

257 attempts, 0 cancelled

Completion

99.6%

of 257 attempts

Complete out of complete and incomplete attempts. Cancelled attempts are listed, never counted.

Evaluated pass rate

100.0%

of 256 evaluations with a verdict

Final attempts that passed, out of pass and code. Lab 0, cancelled 0 and unclassified 0 are shown, never folded in.

Failed after retries

0 of 256

1 failed first time, 1 passed on retry

Changes with a failed boot on this board

0 of 106

Allow-CI+2 for TF-A; linked TF-M runs. 0 with no boot verdict. Linked to a change: 46.5% of 256 evaluations

Last 30 days

Evaluations per day, stacked by final outcome. Hatched means the lab, solid means the code.

Test-case detail: 30 Sep 2026 to 29 Oct 2026. 0 days without data.

History by month

Before the live window we know whether each attempt completed and how retries ended, not why it failed or which change it was. Shaded bands are months with no data held.

Job-level history: 1 Oct 2025 to 6 Sep 2026. Test-case detail: 7 Sep 2026 to 29 Oct 2026. 1 day without data.
All gaps
  • No data held: 28 Feb 2026 to 28 Feb 2026

Units

CI attempts per physical unit, retries included. Passing on another unit can help identify a unit fault. Health checks are fleet health.

1 of 1 first-attempt failures were on stm32mp15x-eval-02; 1 of them passed on another unit.
stm32mp15x-eval-02 77 1 1 0 Complete 28 Oct 16:46
stm32mp15x-eval-01 91 0 0 0 Complete 29 Oct 11:03
stm32mp15x-eval-03 89 0 0 0 Complete 28 Oct 13:52

Evaluations

One row per builder build on this board, newest first, with every attempt. CI runs only; 50 of 256 shown.

Attempts
12 Oct 13:33 tf-a-builder 2584234 52685/4 fix(plat/qemu): make BDF mapping top inclusive integration built refs/changes/85/52685/4
  1. 01Pass
 Pass
12 Oct 13:11 tf-a-builder 2583289 not recorded master built integration
  1. 01Pass
 Pass
12 Oct 13:05 tf-a-builder 2583085 not recorded master built integration
  1. 02Pass
 Pass
12 Oct 11:32 tf-a-builder 2579128 not recorded master built integration
  1. 02Pass
 Pass
12 Oct 10:01 tf-a-builder 2577777 55227/1 refactor(cpus): move C support files into the helpers directory integration built refs/changes/27/55227/1
  1. 03Pass
 Pass
12 Oct 07:24 tf-a-builder 2576821 not recorded master
  1. 02Pass
 Pass
12 Oct 01:24 tf-a-lts2.10-builder 285507 not recorded lts-v2.10
  1. 01Pass
 Pass
12 Oct 00:33 tf-a-lts2.12-builder 341677 not recorded lts-v2.12
  1. 03Pass
 Pass
11 Oct 23:31 tf-a-lts2.14-builder 245357 not recorded lts-v2.14
  1. 01Pass
 Pass
11 Oct 22:29 tf-a-builder 2576342 not recorded master built integration
  1. 03Pass
 Pass
11 Oct 01:21 tf-a-lts2.10-builder 284607 not recorded lts-v2.10
  1. 03Pass
 Pass
11 Oct 00:33 tf-a-lts2.12-builder 340976 not recorded lts-v2.12
  1. 01Pass
 Pass
10 Oct 23:30 tf-a-lts2.14-builder 244456 not recorded lts-v2.14
  1. 01Pass
 Pass
10 Oct 22:33 tf-a-builder 2575693 not recorded master built integration
  1. 01Pass
 Pass
10 Oct 11:26 tf-a-builder 2574946 54926/6 fix(psci): allow OS-initiated mode while other cores are off integration built refs/changes/26/54926/6
  1. 02Pass
 Pass
10 Oct 01:26 tf-a-lts2.10-builder 284010 not recorded lts-v2.10
  1. 02Pass
 Pass
10 Oct 00:37 tf-a-lts2.12-builder 340229 not recorded lts-v2.12
  1. 02Pass
 Pass
9 Oct 23:31 tf-a-lts2.14-builder 243703 not recorded lts-v2.14
  1. 01Pass
 Pass
9 Oct 22:25 tf-a-builder 2573605 not recorded master built integration
  1. 02Pass
 Pass
9 Oct 21:43 tf-a-builder 2572780 55255/1 refactor(qti): set up the delay timer from common code integration built refs/changes/55/55255/1
  1. 03Pass
 Pass
9 Oct 14:59 tf-a-builder 2571869 53535/2 test: default to PSA APIs integration built refs/changes/35/53535/2
  1. 01Pass
 Pass
9 Oct 14:04 tf-a-lts2.10-builder 283219 55248/1 feat(fvp): scale SP_MIN max size based on SRAM size lts-v2.10 built refs/changes/48/55248/1
  1. 01Pass
 Pass
9 Oct 13:27 tf-a-builder 2570576 55211/3 fix(build): always define DYN_DISABLE_AUTH integration built refs/changes/11/55211/3
  1. 03Pass
 Pass
9 Oct 12:03 tf-a-lts2.10-builder 282437 55232/1 chore(fvp): bump maximum permitted Trusted SRAM size lts-v2.10 built refs/changes/32/55232/1
  1. 01Pass
 Pass
9 Oct 10:48 tf-a-builder 2569643 55229/1 fix(lfa): avoid ACTIVATE retry code clash integration built refs/changes/29/55229/1
  1. 02Pass
 Pass
9 Oct 10:08 tf-a-builder 2568896 55227/1 refactor(cpus): move C support files into the helpers directory integration built refs/changes/27/55227/1
  1. 01Pass
 Pass
9 Oct 08:17 tf-a-builder 2567779 55227/1 refactor(cpus): move C support files into the helpers directory integration built refs/changes/27/55227/1
  1. 01Pass
 Pass
9 Oct 06:54 tf-a-builder 2566999 not recorded master
  1. 01Pass
 Pass
9 Oct 01:29 tf-a-lts2.10-builder 281869 not recorded lts-v2.10
  1. 03Pass
 Pass
9 Oct 00:27 tf-a-lts2.12-builder 339141 not recorded lts-v2.12
  1. 03Pass
 Pass
8 Oct 23:31 tf-a-lts2.14-builder 242890 not recorded lts-v2.14
  1. 02Pass
 Pass
8 Oct 22:30 tf-a-builder 2565409 not recorded master built integration
  1. 02Pass
 Pass
8 Oct 21:36 tf-a-builder 2564636 not recorded master built integration
  1. 03Pass
 Pass
8 Oct 17:24 tf-a-lts2.10-builder 281326 55220/1 fix(fvp): absorb BUILD_CPUS_WITH_NO_FVP_MODEL and ENABLE_ERRATA_ALL cores lts-v2.10 built refs/changes/20/55220/1
  1. 01Pass
 Pass
8 Oct 08:46 tf-a-lts2.14-builder 242068 55214/2 refactor(cpus): rename Canyon to C2-Ultra lts-v2.14 built refs/changes/14/55214/2
  1. 02Pass
 Pass
8 Oct 08:19 tf-a-lts2.14-builder 241366 55214/1 refactor(cpus): rename Canyon to C2-Ultra lts-v2.14 built refs/changes/14/55214/1
  1. 01Pass
 Pass
8 Oct 07:15 tf-a-builder 2562008 55188/2 fix(fvp): remove GIC crash reporting integration built refs/changes/88/55188/2
  1. 03Pass
 Pass
8 Oct 06:35 tf-a-builder 2560967 54926/4 fix(psci): allow OS-initiated mode while other cores are off integration built refs/changes/26/54926/4
  1. 03Pass
 Pass
8 Oct 01:42 tf-a-lts2.10-builder 280639 not recorded lts-v2.10
  1. 02Pass
 Pass
8 Oct 00:24 tf-a-lts2.12-builder 338305 not recorded lts-v2.12
  1. 01Pass
 Pass
7 Oct 23:31 tf-a-lts2.14-builder 240692 not recorded lts-v2.14
  1. 03Pass
 Pass
7 Oct 22:27 tf-a-builder 2559897 not recorded master built integration
  1. 03Pass
 Pass
7 Oct 15:08 tf-a-builder 2559348 52109/5 refactor(lfa): add fallback support integration built refs/changes/09/52109/5
  1. 02Pass
 Pass
7 Oct 12:42 tf-a-builder 2558645 54137/7 fix(cpufeat): correctly match the group 3 ID registers space integration built refs/changes/37/54137/7
  1. 01Pass
 Pass
7 Oct 12:22 tf-a-builder 2558107 55180/2 refactor(el3-spmc): remove excess overflow checks integration built refs/changes/80/55180/2
  1. 03Pass
 Pass
7 Oct 10:41 tf-a-builder 2557293 55179/1 fix(firme): fix attestation unmap error handling integration built refs/changes/79/55179/1
  1. 02Pass
 Pass
7 Oct 01:37 tf-a-lts2.10-builder 279846 not recorded lts-v2.10
  1. 03Pass
 Pass
7 Oct 00:32 tf-a-lts2.12-builder 337935 not recorded lts-v2.12
  1. 01Pass
 Pass
6 Oct 23:29 tf-a-lts2.14-builder 239857 not recorded lts-v2.14
  1. 02Pass
 Pass
6 Oct 22:48 tf-a-builder 2551091 not recorded master built integration
  1. 03Pass
 Pass

Show the next 50

Fleet health

Health checks, not CI results. They never count towards any rate on this page.

0 of 19 health checks failed in the last 7 days.

All passed

Showing the latest 19 checks.

  1. Health check 3048913, Complete
  2. Health check 3048929, Complete
  3. Health check 3049026, Complete
  4. Health check 3049357, Complete
  5. Health check 3049372, Complete
  6. Health check 3049381, Complete
  7. Health check 3049689, Complete
  8. Health check 3049704, Complete
  9. Health check 3049713, Complete
  10. Health check 3050138, Complete
  11. Health check 3050209, Complete
  12. Health check 3050446, Complete
  13. Health check 3051130, Complete
  14. Health check 3051145, Complete
  15. Health check 3051208, Complete
  16. Health check 3051681, Complete
  17. Health check 3051699, Complete
  18. Health check 3051754, Complete
  19. Health check 3052227, Complete

One tick per health check, oldest to newest. Each opens its job. Passed Failed Cancelled

Incidents

  1. Lab 17 Sep 2026 to 18 Sep 2026

    LAVA logger DNS failures