TF test results
Synced 12:21 UTC, 3 h ago

Data as of 29 Oct 2026, 12:21 UTC

Last LAVA sync
29 Oct 2026, 12:21 UTC
Last Jenkins sync
29 Oct 2026, 12:23 UTC
Last S3 export sync
7 Oct 2026, 09:53 UTC
Open fetch errors
6,510
About the data
  1. Boards
  2. Arm
  3. N1SDP

N1SDP

, Arm. n1sdp

Live First seen 1 Oct 2025, last seen 29 Oct 2026. 2 units live.

Evaluations

3,321

3,354 attempts, 86 cancelled

Completion

98.6%

of 3,268 attempts

Complete out of complete and incomplete attempts. Cancelled attempts are listed, never counted.

Evaluated pass rate

100.0%

of 773 evaluations with a verdict

Final attempts that passed, out of pass and code. Lab 0, cancelled 86 and unclassified 16 are shown, never folded in.

Failed after retries

16 of 3,321

31 failed first time, 11 passed on retry

Changes with a failed boot on this board

n/a

Not available for this range: change lineage exists for the live window only.

Last 12 months

Evaluations per week, stacked by final outcome. Hatched means the lab, solid means the code.

Job-level history: 27 Oct 2025 to 6 Sep 2026. Test-case detail: 7 Sep 2026 to 29 Oct 2026. 1 day without data.
All gaps
  • No data held: 28 Feb 2026 to 28 Feb 2026

History by month

Before the live window we know whether each attempt completed and how retries ended, not why it failed or which change it was. Shaded bands are months with no data held.

Job-level history: 1 Oct 2025 to 6 Sep 2026. Test-case detail: 7 Sep 2026 to 29 Oct 2026. 1 day without data.
All gaps
  • No data held: 28 Feb 2026 to 28 Feb 2026

Units

CI attempts per physical unit, retries included. Passing on another unit can help identify a unit fault. Health checks are fleet health.

27 of 31 first-attempt failures were on n1sdp-01; 0 of them passed on another unit.
n1sdp-01 3,012 27 0 7 Complete 29 Oct 11:24
n1sdp-02 256 4 3 1 Complete 28 Oct 13:48

Evaluations

One row per builder build on this board, newest first, with every attempt. CI runs only; 50 of 3,321 shown.

Attempts
12 Oct 13:02 tf-a-builder 2582958 not recorded master built integration
  1. 01Pass
 Pass
12 Oct 11:34 tf-a-builder 2579154 not recorded master built integration
  1. 01Pass
 Pass
12 Oct 09:55 tf-a-builder 2577667 55227/1 refactor(cpus): move C support files into the helpers directory integration built refs/changes/27/55227/1
  1. 01Pass
 Pass
12 Oct 07:32 tf-a-builder 2576921 not recorded master
  1. 02Pass
 Pass
12 Oct 02:19 tf-a-lts2.8-builder 225255 not recorded lts-v2.8
  1. 02Pass
 Pass
12 Oct 01:28 tf-a-lts2.10-builder 285687 not recorded lts-v2.10
  1. 02Pass
 Pass
12 Oct 01:09 tf-a-lts2.12-builder 341861 not recorded lts-v2.12
  1. 02Pass
 Pass
12 Oct 00:32 tf-a-lts2.12-builder 341622 not recorded lts-v2.12
  1. 01Pass
 Pass
12 Oct 00:08 tf-a-lts2.14-builder 245556 not recorded lts-v2.14
  1. 02Pass
 Pass
11 Oct 23:26 tf-a-lts2.14-builder 245109 not recorded lts-v2.14
  1. 01Pass
 Pass
11 Oct 23:04 tf-a-builder 2576644 not recorded master built integration
  1. 01Pass
 Pass
11 Oct 23:02 tf-a-builder 2576597 not recorded master built integration
  1. 01Pass
 Pass
11 Oct 22:32 tf-a-builder 2576408 not recorded master built integration
  1. 02Pass
 Pass
11 Oct 02:30 tf-a-lts2.8-builder 225028 not recorded lts-v2.8
  1. 02Pass
 Pass
11 Oct 01:32 tf-a-lts2.10-builder 284867 not recorded lts-v2.10
  1. 02Pass
 Pass
11 Oct 01:16 tf-a-lts2.12-builder 341109 not recorded lts-v2.12
  1. 01Pass
 Pass
11 Oct 00:29 tf-a-lts2.12-builder 340865 not recorded lts-v2.12
  1. 01Pass
 Pass
11 Oct 00:10 tf-a-lts2.14-builder 244747 not recorded lts-v2.14
  1. 01Pass
 Pass
10 Oct 23:26 tf-a-lts2.14-builder 244261 not recorded lts-v2.14
  1. 02Pass
 Pass
10 Oct 23:04 tf-a-builder 2575797 not recorded master built integration
  1. 02Pass
 Pass
10 Oct 23:00 tf-a-builder 2575753 not recorded master built integration
  1. 01Pass
 Pass
10 Oct 22:27 tf-a-builder 2575527 not recorded master built integration
  1. 02Pass
 Pass
10 Oct 11:25 tf-a-builder 2574920 54926/6 fix(psci): allow OS-initiated mode while other cores are off integration built refs/changes/26/54926/6
  1. 02Pass
 Pass
10 Oct 02:27 tf-a-lts2.8-builder 224366 not recorded lts-v2.8
  1. 02Pass
 Pass
10 Oct 01:24 tf-a-lts2.10-builder 283894 not recorded lts-v2.10
  1. 01Pass
 Pass
10 Oct 01:18 tf-a-lts2.12-builder 340357 not recorded lts-v2.12
  1. 01Pass
 Pass
10 Oct 00:31 tf-a-lts2.12-builder 340056 not recorded lts-v2.12
  1. 02Pass
 Pass
10 Oct 00:12 tf-a-lts2.14-builder 243938 not recorded lts-v2.14
  1. 01Pass
 Pass
9 Oct 23:27 tf-a-lts2.14-builder 243544 not recorded lts-v2.14
  1. 01Pass
 Pass
9 Oct 22:59 tf-a-builder 2573831 not recorded master built integration
  1. 01Pass
 Pass
9 Oct 22:59 tf-a-builder 2573834 not recorded master built integration
  1. 02Pass
 Pass
9 Oct 22:28 tf-a-builder 2573674 not recorded master built integration
  1. 01Pass
 Pass
9 Oct 21:44 tf-a-builder 2572757 55255/1 refactor(qti): set up the delay timer from common code integration built refs/changes/55/55255/1
  1. 02Pass
 Pass
9 Oct 13:54 tf-a-lts2.10-builder 283004 55248/1 feat(fvp): scale SP_MIN max size based on SRAM size lts-v2.10 built refs/changes/48/55248/1
  1. 01Pass
 Pass
9 Oct 13:31 tf-a-builder 2570726 55211/3 fix(build): always define DYN_DISABLE_AUTH integration built refs/changes/11/55211/3
  1. 02Pass
 Pass
9 Oct 13:17 tf-a-lts2.8-builder 223754 55233/1 feat(fvp): scale SP_MIN max size based on SRAM size lts-v2.8 built refs/changes/33/55233/1
  1. 02Pass
 Pass
9 Oct 12:02 tf-a-lts2.10-builder 282403 55232/1 chore(fvp): bump maximum permitted Trusted SRAM size lts-v2.10 built refs/changes/32/55232/1
  1. 01Pass
 Pass
9 Oct 11:29 tf-a-lts2.8-builder 223172 55231/1 chore(fvp): bump maximum permitted Trusted SRAM size lts-v2.8 built refs/changes/31/55231/1
  1. 02Pass
 Pass
9 Oct 10:59 tf-a-lts2.8-builder 222568 55231/1 chore(fvp): bump maximum permitted Trusted SRAM size lts-v2.8 built refs/changes/31/55231/1
  1. 01Pass
 Pass
9 Oct 10:46 tf-a-builder 2569627 55229/1 fix(lfa): avoid ACTIVATE retry code clash integration built refs/changes/29/55229/1
  1. 01Pass
 Pass
9 Oct 09:57 tf-a-lts2.8-builder 222308 55228/2 fix(fvp): absorb BUILD_CPUS_WITH_NO_FVP_MODEL and ENABLE_ERRATA_ALL CPUs lts-v2.8 built refs/changes/28/55228/2
  1. 02Pass
 Pass
9 Oct 09:54 tf-a-builder 2568633 55227/1 refactor(cpus): move C support files into the helpers directory integration built refs/changes/27/55227/1
  1. 01Pass
 Pass
9 Oct 09:40 tf-a-lts2.8-builder 221682 55228/1 fix(fvp): absorb BUILD_CPUS_WITH_NO_FVP_MODEL and ENABLE_ERRATA_ALL CPUs lts-v2.8 built refs/changes/28/55228/1
  1. 02Pass
 Pass
9 Oct 09:29 tf-a-lts2.8-builder 221092 55228/1 fix(fvp): absorb BUILD_CPUS_WITH_NO_FVP_MODEL and ENABLE_ERRATA_ALL CPUs lts-v2.8 built refs/changes/28/55228/1
  1. 02Pass
 Pass
9 Oct 08:16 tf-a-builder 2567711 55227/1 refactor(cpus): move C support files into the helpers directory integration built refs/changes/27/55227/1
  1. 01Pass
 Pass
9 Oct 06:48 tf-a-builder 2566850 not recorded master
  1. 02Pass
 Pass
9 Oct 02:25 tf-a-lts2.8-builder 220477 not recorded lts-v2.8
  1. 01Pass
 Pass
9 Oct 01:29 tf-a-lts2.10-builder 281854 not recorded lts-v2.10
  1. 01Pass
 Pass
9 Oct 01:13 tf-a-lts2.12-builder 339605 not recorded lts-v2.12
  1. 02Pass
 Pass
9 Oct 00:40 tf-a-lts2.12-builder 339471 not recorded lts-v2.12
  1. 02Pass
 Pass

Show the next 50

Fleet health

Health checks, not CI results. They never count towards any rate on this page.

0 of 13 health checks failed in the last 7 days.

All passed

Showing the latest 13 checks.

  1. Health check 3048915, Complete
  2. Health check 3048928, Complete
  3. Health check 3049359, Complete
  4. Health check 3049371, Complete
  5. Health check 3049691, Complete
  6. Health check 3049703, Complete
  7. Health check 3050180, Complete
  8. Health check 3050208, Complete
  9. Health check 3051132, Complete
  10. Health check 3051144, Complete
  11. Health check 3051683, Complete
  12. Health check 3051698, Complete
  13. Health check 3052304, Complete

One tick per health check, oldest to newest. Each opens its job. Passed Failed Cancelled

Incidents

  1. Lab 17 Sep 2026 to 18 Sep 2026

    LAVA logger DNS failures