TF test results
Synced 12:21 UTC, under 1 h ago

Data as of 31 Oct 2026, 12:21 UTC

Last LAVA sync
31 Oct 2026, 12:21 UTC
Last Jenkins sync
31 Oct 2026, 12:22 UTC
Last S3 export sync
7 Oct 2026, 09:53 UTC
Open fetch errors
6,510
About the data
  1. Boards
  2. Arm
  3. N1SDP

N1SDP

, Arm. n1sdp

Live First seen 1 Oct 2025, last seen 31 Oct 2026. 2 units live.

Evaluations

3,356

3,389 attempts, 86 cancelled

Completion

98.6%

of 3,303 attempts

Complete out of complete and incomplete attempts. Cancelled attempts are listed, never counted.

Evaluated pass rate

100.0%

of 811 evaluations with a verdict

Final attempts that passed, out of pass and code. Lab 0, cancelled 86 and unclassified 16 are shown, never folded in.

Failed after retries

16 of 3,356

31 failed first time, 11 passed on retry

Changes with a failed boot on this board

n/a

Not available for this range: change lineage exists for the live window only.

Last 12 months

Evaluations per week, stacked by final outcome. Hatched means the lab, solid means the code.

Job-level history: 27 Oct 2025 to 6 Sep 2026. Test-case detail: 7 Sep 2026 to 31 Oct 2026. 1 day without data.
All gaps
  • No data held: 28 Feb 2026 to 28 Feb 2026

History by month

Before the live window we know whether each attempt completed and how retries ended, not why it failed or which change it was. Shaded bands are months with no data held.

Job-level history: 1 Oct 2025 to 6 Sep 2026. Test-case detail: 7 Sep 2026 to 31 Oct 2026. 1 day without data.
All gaps
  • No data held: 28 Feb 2026 to 28 Feb 2026

Units

CI attempts per physical unit, retries included. Passing on another unit can help identify a unit fault. Health checks are fleet health.

27 of 31 first-attempt failures were on n1sdp-01; 0 of them passed on another unit.

n1sdp-01 3,031 27 0 7 Complete 31 Oct 11:24
n1sdp-02 272 4 3 1 Complete 30 Oct 13:49

Evaluations

One row per builder build on this board, newest first, with every attempt. CI runs only; 50 of 3,006 shown.

Attempts
28 Sep 10:02 tf-a-builder 2497159 not recorded Branch not recorded
  1. 01Pass
Pass
28 Sep 09:37 tf-a-builder 2495725 not recorded Branch not recorded
  1. 01Pass
Pass
28 Sep 09:04 tf-a-builder 2494048 54479/2 fix(cpus): add workarounds for C1-Pro errata 3679375 and 3806276 integration built refs/changes/79/54479/2
  1. 01Pass
Pass
28 Sep 02:18 tf-a-lts2.8-builder 212472 not recorded lts-v2.8
  1. 01Pass
Pass
28 Sep 01:16 tf-a-lts2.10-builder 272238 not recorded lts-v2.10
  1. 01Pass
Pass
28 Sep 00:33 tf-a-lts2.12-builder 330557 not recorded lts-v2.12
  1. 01Pass
Pass
27 Sep 23:41 tf-a-lts2.14-builder 229329 not recorded lts-v2.14
  1. 01Pass
Pass
27 Sep 23:00 tf-a-builder 2493718 not recorded Branch not recorded
  1. 01Pass
Pass
27 Sep 02:16 tf-a-lts2.8-builder 211866 not recorded lts-v2.8
  1. 01Pass
Pass
27 Sep 01:00 tf-a-lts2.12-builder 329885 not recorded lts-v2.12
  1. 01Pass
Pass
27 Sep 00:33 tf-a-lts2.12-builder 329787 not recorded lts-v2.12
  1. 01Pass
Pass
27 Sep 00:10 tf-a-lts2.14-builder 228603 not recorded lts-v2.14
  1. 01Pass
Pass
26 Sep 23:37 tf-a-lts2.14-builder 228497 not recorded lts-v2.14
  1. 01Pass
Pass
26 Sep 23:01 tf-a-builder 2491396 not recorded Branch not recorded
  1. 01Pass
Pass
26 Sep 17:20 tf-a-lts2.14-builder 227091 54891/2 chore(deps-dev): Bump commitizen lts-v2.14 built refs/changes/91/54891/2
  1. 01Pass
Pass
26 Sep 14:41 tf-a-lts2.14-builder 225441 54891/1 chore(deps-dev): Bump commitizen lts-v2.14 built refs/changes/91/54891/1
  1. 01Pass
Pass
26 Sep 06:27 tf-a-builder 2490318 not recorded Branch not recorded
  1. 01Pass
Pass
26 Sep 02:18 tf-a-lts2.8-builder 211511 not recorded lts-v2.8
  1. 01Pass
Pass
26 Sep 00:06 tf-a-lts2.14-builder 224989 not recorded lts-v2.14
  1. 01Pass
Pass
25 Sep 23:26 tf-a-lts2.14-builder 224707 not recorded lts-v2.14
  1. 01Pass
Pass
25 Sep 23:07 tf-a-builder 2489795 not recorded Branch not recorded
  1. 01Pass
Pass
25 Sep 22:29 tf-a-builder 2489470 not recorded Branch not recorded
  1. 01Pass
Pass
25 Sep 15:24 tf-a-builder 2488698 54828/1 fix(k3low): use size_t for fwls index integration built refs/changes/28/54828/1
  1. 01Pass
Pass
25 Sep 12:25 tf-a-lts2.8-builder 211077 54812/4 fix(mediatek): enable missing Cortex-A78 errata for MT8195 lts-v2.8 built refs/changes/12/54812/4
  1. 01Pass
Pass
25 Sep 12:13 tf-a-lts2.8-builder 210402 54812/4 fix(mediatek): enable missing Cortex-A78 errata for MT8195 lts-v2.8 built refs/changes/12/54812/4
  1. 01Pass
Pass
25 Sep 09:59 tf-a-lts2.8-builder 208814 54812/3 fix(mediatek): enable missing Cortex-A78 errata for MT8195 lts-v2.8 built refs/changes/12/54812/3
  1. 01Pass
Pass
25 Sep 09:35 tf-a-builder 2484294 54860/1 refactor(cpus): rename Canyon to C2-Ultra integration built refs/changes/60/54860/1
  1. 01Pass
Pass
25 Sep 08:30 tf-a-builder 2482067 54136/4 fix(el3-runtime): harden against sysreg accesses targeting XZR integration built refs/changes/36/54136/4
  1. 01Pass
Pass
25 Sep 07:23 tf-a-builder 2480133 54843/1 fix(delay-timer): count timeouts in the configured frequency integration built refs/changes/43/54843/1
  1. 01Pass
Pass
25 Sep 01:33 tf-a-lts2.12-builder 328433 not recorded lts-v2.12
  1. 01Pass
Pass
25 Sep 00:19 tf-a-lts2.12-builder 328154 not recorded lts-v2.12
  1. 01Pass
Pass
24 Sep 23:32 tf-a-lts2.14-builder 223728 not recorded lts-v2.14
  1. 01Pass
Pass
24 Sep 23:26 tf-a-builder 2478819 not recorded Branch not recorded
  1. 01Pass
Pass
24 Sep 23:20 tf-a-lts2.8-builder 207865 54812/2 fix(mediatek): enable missing Cortex-A78 errata for MT8195 lts-v2.8 built refs/changes/12/54812/2
  1. 01Pass
Pass
24 Sep 23:12 tf-a-lts2.8-builder 207500 54807/3 fix(fdt-wrappers): reject negative cell counts lts-v2.8 built refs/changes/07/54807/3
  1. 01Pass
Pass
24 Sep 23:05 tf-a-lts2.8-builder 207180 54812/2 fix(mediatek): enable missing Cortex-A78 errata for MT8195 lts-v2.8 built refs/changes/12/54812/2
  1. 01Pass
Pass
24 Sep 22:44 tf-a-lts2.8-builder 206222 54807/3 fix(fdt-wrappers): reject negative cell counts lts-v2.8 built refs/changes/07/54807/3
  1. 01Pass
Pass
24 Sep 16:24 tf-a-lts2.8-builder 205733 54812/1 fix(mediatek): enable missing Cortex-A78 errata for MT8195 lts-v2.8 built refs/changes/12/54812/1
  1. 01Pass
Pass
24 Sep 15:30 tf-a-lts2.8-builder 203888 54807/1 fix(fdt-wrappers): reject negative cell counts lts-v2.8 built refs/changes/07/54807/1
  1. 01Pass
Pass
24 Sep 15:14 tf-a-lts2.12-builder 327655 54794/1 fix(qti): harden mem_assign parameter handling lts-v2.12 built refs/changes/94/54794/1
  1. 01Pass
Pass
24 Sep 14:11 tf-a-builder 2477082 53399/15 feat(rdv3): add FIRME attestation platform hooks integration built refs/changes/99/53399/15
  1. 01Pass
Pass
24 Sep 09:32 tf-a-builder 2475586 54022/4 feat(smc-validation): make NS range hook a mandatory porting interface integration built refs/changes/22/54022/4
  1. 01Pass
Pass
24 Sep 06:37 tf-a-lts2.14-builder 223345 54772/1 fix(rdaspen): correct PSCI power domain topology lts-v2.14 built refs/changes/72/54772/1
  1. 01Pass
Pass
24 Sep 02:31 tf-a-lts2.8-builder 202417 not recorded lts-v2.8
  1. 01Pass
Pass
24 Sep 01:21 tf-a-lts2.10-builder 269184 not recorded lts-v2.10
  1. 01Pass
Pass
24 Sep 01:05 tf-a-lts2.12-builder 327035 not recorded lts-v2.12
  1. 01Pass
Pass
24 Sep 00:26 tf-a-lts2.12-builder 326595 not recorded lts-v2.12
  1. 01Pass
Pass
23 Sep 23:56 tf-a-lts2.14-builder 222652 not recorded lts-v2.14
  1. 01Pass
Pass
23 Sep 23:18 tf-a-lts2.14-builder 222239 not recorded lts-v2.14
  1. 01Pass
Pass
23 Sep 23:06 tf-a-builder 2474266 not recorded Branch not recorded
  1. 01Pass
Pass

Show the next 50

Fleet health

Health checks, not CI results. They never count towards any rate on this page.

0 of 13 health checks failed in the last 7 days.

All passed

Showing the latest 13 checks.

  1. Health check 3049691, Complete
  2. Health check 3049703, Complete
  3. Health check 3050180, Complete
  4. Health check 3050208, Complete
  5. Health check 3051132, Complete
  6. Health check 3051144, Complete
  7. Health check 3051683, Complete
  8. Health check 3051698, Complete
  9. Health check 3052304, Complete
  10. Health check 3052319, Complete
  11. Health check 3052978, Complete
  12. Health check 3053205, Complete
  13. Health check 3053837, Complete

One tick per health check, oldest to newest. Each opens its job. Passed Failed Cancelled

Incidents

  1. Lab 17 Sep 2026 to 18 Sep 2026

    LAVA logger DNS failures