TF test results
Synced 06:22 UTC, 2 h ago

Data as of 30 Oct 2026, 06:22 UTC

Last LAVA sync
30 Oct 2026, 06:22 UTC
Last Jenkins sync
30 Oct 2026, 06:24 UTC
Last S3 export sync
7 Oct 2026, 09:53 UTC
Open fetch errors
6,510
About the data
  1. Boards
  2. Google ChromeOS
  3. Asurada (MT8192)

Asurada (MT8192)

MT8192, Asurada, Chromebook. mt8192-asurada-rev1

Live First seen 1 Oct 2025, last seen 30 Oct 2026. 3 units live.

Evaluations

3,164

3,255 attempts, 0 cancelled

Completion

95.8%

of 3,255 attempts

Complete out of complete and incomplete attempts. Cancelled attempts are listed, never counted.

Evaluated pass rate

100.0%

of 568 evaluations with a verdict

Final attempts that passed, out of pass and code. Lab 2, cancelled 0 and unclassified 44 are shown, never folded in.

Failed after retries

46 of 3,164

91 failed first time, 45 passed on retry

Changes with a failed boot on this board

n/a

Not available for this range: change lineage exists for the live window only.

Last 12 months

Evaluations per week, stacked by final outcome. Hatched means the lab, solid means the code.

Job-level history: 27 Oct 2025 to 6 Sep 2026. Test-case detail: 7 Sep 2026 to 30 Oct 2026. 1 day without data.
All gaps
  • No data held: 28 Feb 2026 to 28 Feb 2026

History by month

Before the live window we know whether each attempt completed and how retries ended, not why it failed or which change it was. Shaded bands are months with no data held.

Job-level history: 1 Oct 2025 to 6 Sep 2026. Test-case detail: 7 Sep 2026 to 30 Oct 2026. 1 day without data.
All gaps
  • No data held: 28 Feb 2026 to 28 Feb 2026

Units

CI attempts per physical unit, retries included. Passing on another unit can help identify a unit fault. Health checks are fleet health.

47 of 91 first-attempt failures were on asurada-01; 34 of them passed on another unit.
asurada-01 788 47 34 1 Complete 30 Oct 01:40
asurada-03 1,246 26 6 0 Complete 29 Oct 10:38
asurada-02 1,221 18 4 0 Complete 29 Oct 22:49

Evaluations

One row per builder build on this board, newest first, with every attempt. CI runs only; 50 of 3,164 shown.

Attempts
26 Sep 14:40 tf-a-lts2.14-builder 225466 54891/1 chore(deps-dev): Bump commitizen lts-v2.14 built refs/changes/91/54891/1
  1. 02Pass
 Pass
26 Sep 06:15 tf-a-builder 2489918 not recorded Branch not recorded
  1. 01Pass
 Pass
26 Sep 02:13 tf-a-lts2.8-builder 211338 not recorded lts-v2.8
  1. 01Pass
 Pass
26 Sep 01:39 tf-a-lts2.10-builder 271086 not recorded lts-v2.10
  1. 01Pass
 Pass
26 Sep 00:23 tf-a-lts2.12-builder 328834 not recorded lts-v2.12
  1. 03Pass
 Pass
25 Sep 23:13 tf-a-lts2.14-builder 224380 not recorded lts-v2.14
  1. 03Pass
 Pass
25 Sep 22:14 tf-a-builder 2489177 not recorded Branch not recorded
  1. 03Pass
 Pass
25 Sep 15:30 tf-a-builder 2488868 54828/1 fix(k3low): use size_t for fwls index integration built refs/changes/28/54828/1
  1. 01Pass
 Pass
25 Sep 15:02 tf-a-builder 2488168 54860/3 refactor(cpus): rename Canyon to C2-Ultra integration built refs/changes/60/54860/3
  1. 03Pass
 Pass
25 Sep 12:44 tf-a-builder 2486433 54873/1 feat(lemans): add FF-A/SPMD support with OP-TEE as S-EL1 SPMC integration built refs/changes/73/54873/1
  1. 02Pass
 Pass
25 Sep 12:31 tf-a-lts2.8-builder 211166 54812/4 fix(mediatek): enable missing Cortex-A78 errata for MT8195 lts-v2.8 built refs/changes/12/54812/4
  1. 02Pass
 Pass
25 Sep 12:23 tf-a-lts2.8-builder 210978 54812/4 fix(mediatek): enable missing Cortex-A78 errata for MT8195 lts-v2.8 built refs/changes/12/54812/4
  1. 03Pass
 Pass
25 Sep 12:17 tf-a-lts2.8-builder 210616 54810/4 fix(xilinx): allow secure access to IPI channels lts-v2.8 built refs/changes/10/54810/4
  1. 02Pass
 Pass
25 Sep 10:19 tf-a-lts2.8-builder 209553 54812/3 fix(mediatek): enable missing Cortex-A78 errata for MT8195 lts-v2.8 built refs/changes/12/54812/3
  1. 01Pass
 Pass
25 Sep 10:13 tf-a-lts2.8-builder 209411 54812/3 fix(mediatek): enable missing Cortex-A78 errata for MT8195 lts-v2.8 built refs/changes/12/54812/3
  1. 03Pass
 Pass
25 Sep 09:34 tf-a-builder 2484327 54860/1 refactor(cpus): rename Canyon to C2-Ultra integration built refs/changes/60/54860/1
  1. 03Pass
 Pass
25 Sep 09:05 tf-a-builder 2482511 54859/1 fix(cpufeat): remove the `sev` from spin_unlock() integration built refs/changes/59/54859/1
  1. 03Pass
 Pass
25 Sep 08:22 tf-a-builder 2481841 54136/4 fix(el3-runtime): harden against sysreg accesses targeting XZR integration built refs/changes/36/54136/4
  1. 03Pass
 Pass
25 Sep 07:33 tf-a-builder 2480447 54843/1 fix(delay-timer): count timeouts in the configured frequency integration built refs/changes/43/54843/1
  1. 03Pass
 Pass
25 Sep 05:32 tf-a-builder 2479896 54848/1 docs(qti): add Arduino VENTUNO Q documentation integration built refs/changes/48/54848/1
  1. 03Pass
 Pass
25 Sep 02:29 tf-a-lts2.8-builder 208420 not recorded lts-v2.8
  1. 03Pass
 Pass
25 Sep 01:35 tf-a-lts2.10-builder 270308 not recorded lts-v2.10
  1. 02Pass
 Pass
25 Sep 00:14 tf-a-lts2.12-builder 327942 not recorded lts-v2.12
  1. 02Pass
 Pass
24 Sep 23:34 tf-a-lts2.14-builder 223812 not recorded lts-v2.14
  1. 03Pass
 Pass
24 Sep 23:12 tf-a-lts2.8-builder 207532 54812/2 fix(mediatek): enable missing Cortex-A78 errata for MT8195 lts-v2.8 built refs/changes/12/54812/2
  1. 03Pass
 Pass
24 Sep 23:05 tf-a-lts2.8-builder 207185 54812/2 fix(mediatek): enable missing Cortex-A78 errata for MT8195 lts-v2.8 built refs/changes/12/54812/2
  1. 02Pass
 Pass
24 Sep 23:03 tf-a-lts2.8-builder 207103 54807/3 fix(fdt-wrappers): reject negative cell counts lts-v2.8 built refs/changes/07/54807/3
  1. 03Pass
 Pass
24 Sep 22:53 tf-a-lts2.8-builder 206614 54807/3 fix(fdt-wrappers): reject negative cell counts lts-v2.8 built refs/changes/07/54807/3
  1. 03Pass
 Pass
24 Sep 22:28 tf-a-builder 2478689 not recorded Branch not recorded
  1. 02Pass
 Pass
24 Sep 16:23 tf-a-lts2.8-builder 205720 54812/1 fix(mediatek): enable missing Cortex-A78 errata for MT8195 lts-v2.8 built refs/changes/12/54812/1
  1. 03Pass
 Pass
24 Sep 15:37 tf-a-lts2.8-builder 204110 54807/1 fix(fdt-wrappers): reject negative cell counts lts-v2.8 built refs/changes/07/54807/1
  1. 03Pass
 Pass
24 Sep 15:13 tf-a-lts2.8-builder 203555 54820/1 fix(cpus): remove stray conflict marker in cortex_a77.h lts-v2.8 built refs/changes/20/54820/1
  1. 02Pass
 Pass
24 Sep 15:09 tf-a-lts2.12-builder 327562 54794/1 fix(qti): harden mem_assign parameter handling lts-v2.12 built refs/changes/94/54794/1
  1. 01Pass
 Pass
24 Sep 14:54 tf-a-lts2.8-builder 202867 54799/1 fix(qti): harden mem_assign parameter handling lts-v2.8 built refs/changes/99/54799/1
  1. 03Pass
 Pass
24 Sep 14:25 tf-a-builder 2477428 53399/15 feat(rdv3): add FIRME attestation platform hooks integration built refs/changes/99/53399/15
  1. 02Pass
 Pass
24 Sep 09:25 tf-a-builder 2475356 54022/4 feat(smc-validation): make NS range hook a mandatory porting interface integration built refs/changes/22/54022/4
  1. 03Pass
 Pass
24 Sep 06:36 tf-a-lts2.14-builder 223336 54772/1 fix(rdaspen): correct PSCI power domain topology lts-v2.14 built refs/changes/72/54772/1
  1. 02Pass
 Pass
24 Sep 02:20 tf-a-lts2.8-builder 202179 not recorded lts-v2.8
  1. 02Pass
 Pass
24 Sep 01:39 tf-a-lts2.10-builder 269504 not recorded lts-v2.10
  1. 02Pass
 Pass
24 Sep 00:33 tf-a-lts2.12-builder 326828 not recorded lts-v2.12
  1. 02Pass
 Pass
23 Sep 23:17 tf-a-lts2.14-builder 222250 not recorded lts-v2.14
  1. 03Pass
 Pass
23 Sep 22:14 tf-a-builder 2473597 not recorded Branch not recorded
  1. 02Pass
 Pass
23 Sep 18:21 tf-a-builder 2473376 54782/3 fix(rv1126b): use #if defined for IMAGE_BL flags integration built refs/changes/82/54782/3
  1. 01Pass
 Pass
23 Sep 16:53 tf-a-builder 2472642 54787/1 fix(build): add a default value for XLAT_TABLES_LIB_V2 integration built refs/changes/87/54787/1
  1. 03Pass
 Pass
23 Sep 15:22 tf-a-builder 2471155 54783/1 fix(build): move DSU flags to Makefile integration built refs/changes/83/54783/1
  1. 03Pass
 Pass
23 Sep 12:35 tf-a-builder 2469409 53043/4 feat(gicv3): force IGRPMODR=0 when defaulting interrupts to Group-1NS integration built refs/changes/43/53043/4
  1. 02Pass
 Pass
23 Sep 12:10 tf-a-builder 2468308 53043/4 feat(gicv3): force IGRPMODR=0 when defaulting interrupts to Group-1NS integration built refs/changes/43/53043/4
  1. 01Pass
 Pass
23 Sep 11:52 tf-a-builder 2467877 54760/1 refactor(qti): extract common Hoya macros into hoya_def.h integration built refs/changes/60/54760/1
  1. 01Pass
 Pass
23 Sep 08:24 tf-a-builder 2461519 54022/3 feat(smc-validation): make NS range hook a mandatory porting interface integration built refs/changes/22/54022/3
  1. 03Pass
 Pass
23 Sep 08:07 tf-a-lts2.14-builder 221667 54758/1 fix(qemu): add TB_FW_CONFIG_SIZE and TOS_FW_CONFIG_SIZE defines lts-v2.14 built refs/changes/58/54758/1
  1. 02Pass
 Pass

Show the next 50

Fleet health

Health checks, not CI results. They never count towards any rate on this page.

0 of 19 health checks failed in the last 7 days.

All passed

Showing the latest 19 checks.

  1. Health check 3049245, Complete
  2. Health check 3049354, Complete
  3. Health check 3049430, Complete
  4. Health check 3049600, Complete
  5. Health check 3049686, Complete
  6. Health check 3049766, Complete
  7. Health check 3049924, Complete
  8. Health check 3050115, Complete
  9. Health check 3050684, Complete
  10. Health check 3050847, Complete
  11. Health check 3051062, Complete
  12. Health check 3051309, Complete
  13. Health check 3051512, Complete
  14. Health check 3051678, Complete
  15. Health check 3051853, Complete
  16. Health check 3052025, Complete
  17. Health check 3052211, Complete
  18. Health check 3052556, Complete
  19. Health check 3052773, Complete

One tick per health check, oldest to newest. Each opens its job. Passed Failed Cancelled

Incidents

  1. Lab 17 Sep 2026 to 18 Sep 2026

    LAVA logger DNS failures