TF test results
Synced 18:19 UTC, under 1 h ago

Data as of 29 Oct 2026, 18:19 UTC

Last LAVA sync
29 Oct 2026, 18:19 UTC
Last Jenkins sync
29 Oct 2026, 18:22 UTC
Last S3 export sync
7 Oct 2026, 09:53 UTC
Open fetch errors
6,509
About the data
  1. Boards
  2. Google ChromeOS
  3. Asurada (MT8192)

Asurada (MT8192)

MT8192, Asurada, Chromebook. mt8192-asurada-rev1

Live First seen 1 Oct 2025, last seen 29 Oct 2026. 3 units live.

Evaluations

3,167

3,258 attempts, 0 cancelled

Completion

95.8%

of 3,258 attempts

Complete out of complete and incomplete attempts. Cancelled attempts are listed, never counted.

Evaluated pass rate

100.0%

of 562 evaluations with a verdict

Final attempts that passed, out of pass and code. Lab 2, cancelled 0 and unclassified 44 are shown, never folded in.

Failed after retries

46 of 3,167

91 failed first time, 45 passed on retry

Changes with a failed boot on this board

n/a

Not available for this range: change lineage exists for the live window only.

Last 12 months

Evaluations per week, stacked by final outcome. Hatched means the lab, solid means the code.

Job-level history: 27 Oct 2025 to 6 Sep 2026. Test-case detail: 7 Sep 2026 to 29 Oct 2026. 1 day without data.
All gaps
  • No data held: 28 Feb 2026 to 28 Feb 2026

History by month

Before the live window we know whether each attempt completed and how retries ended, not why it failed or which change it was. Shaded bands are months with no data held.

Job-level history: 1 Oct 2025 to 6 Sep 2026. Test-case detail: 7 Sep 2026 to 29 Oct 2026. 1 day without data.
All gaps
  • No data held: 28 Feb 2026 to 28 Feb 2026

Units

CI attempts per physical unit, retries included. Passing on another unit can help identify a unit fault. Health checks are fleet health.

47 of 91 first-attempt failures were on asurada-01; 34 of them passed on another unit.
asurada-01 790 47 34 1 Complete 29 Oct 01:40
asurada-03 1,245 26 6 0 Complete 29 Oct 10:38
asurada-02 1,223 18 4 0 Complete 28 Oct 22:49

Evaluations

One row per builder build on this board, newest first, with every attempt. CI runs only; 50 of 3,167 shown.

Attempts
9 Oct 23:28 tf-a-lts2.14-builder 243611 not recorded lts-v2.14
  1. 03Pass
 Pass
9 Oct 22:25 tf-a-builder 2573613 not recorded master built integration
  1. 02Pass
 Pass
9 Oct 21:39 tf-a-builder 2572661 55255/1 refactor(qti): set up the delay timer from common code integration built refs/changes/55/55255/1
  1. 03Pass
 Pass
9 Oct 14:52 tf-a-builder 2571742 53535/2 test: default to PSA APIs integration built refs/changes/35/53535/2
  1. 02Pass
 Pass
9 Oct 14:17 tf-a-lts2.10-builder 283441 55248/1 feat(fvp): scale SP_MIN max size based on SRAM size lts-v2.10 built refs/changes/48/55248/1
  1. 02Pass
 Pass
9 Oct 13:30 tf-a-builder 2570713 55211/3 fix(build): always define DYN_DISABLE_AUTH integration built refs/changes/11/55211/3
  1. 03Pass
 Pass
9 Oct 13:20 tf-a-lts2.8-builder 223883 55233/1 feat(fvp): scale SP_MIN max size based on SRAM size lts-v2.8 built refs/changes/33/55233/1
  1. 03Pass
 Pass
9 Oct 12:24 tf-a-lts2.10-builder 282818 55232/1 chore(fvp): bump maximum permitted Trusted SRAM size lts-v2.10 built refs/changes/32/55232/1
  1. 03Pass
 Pass
9 Oct 11:45 tf-a-lts2.8-builder 223374 55231/1 chore(fvp): bump maximum permitted Trusted SRAM size lts-v2.8 built refs/changes/31/55231/1
  1. 02Pass
 Pass
9 Oct 10:53 tf-a-lts2.8-builder 222424 55231/1 chore(fvp): bump maximum permitted Trusted SRAM size lts-v2.8 built refs/changes/31/55231/1
  1. 03Pass
 Pass
9 Oct 10:17 tf-a-builder 2569005 55229/1 fix(lfa): avoid ACTIVATE retry code clash integration built refs/changes/29/55229/1
  1. 03Pass
 Pass
9 Oct 09:56 tf-a-lts2.8-builder 222290 55228/2 fix(fvp): absorb BUILD_CPUS_WITH_NO_FVP_MODEL and ENABLE_ERRATA_ALL CPUs lts-v2.8 built refs/changes/28/55228/2
  1. 02Pass
 Pass
9 Oct 09:54 tf-a-builder 2568678 55227/1 refactor(cpus): move C support files into the helpers directory integration built refs/changes/27/55227/1
  1. 03Pass
 Pass
9 Oct 09:38 tf-a-lts2.8-builder 221574 55228/1 fix(fvp): absorb BUILD_CPUS_WITH_NO_FVP_MODEL and ENABLE_ERRATA_ALL CPUs lts-v2.8 built refs/changes/28/55228/1
  1. 02Pass
 Pass
9 Oct 09:32 tf-a-lts2.8-builder 221231 55228/1 fix(fvp): absorb BUILD_CPUS_WITH_NO_FVP_MODEL and ENABLE_ERRATA_ALL CPUs lts-v2.8 built refs/changes/28/55228/1
  1. 02Pass
 Pass
9 Oct 08:14 tf-a-builder 2567698 55227/1 refactor(cpus): move C support files into the helpers directory integration built refs/changes/27/55227/1
  1. 03Pass
 Pass
9 Oct 06:47 tf-a-builder 2566856 not recorded master
  1. 03Pass
 Pass
9 Oct 02:33 tf-a-lts2.8-builder 220628 not recorded lts-v2.8
  1. 03Pass
 Pass
9 Oct 01:20 tf-a-lts2.10-builder 281565 not recorded lts-v2.10
  1. 03Pass
 Pass
9 Oct 00:34 tf-a-lts2.12-builder 339320 not recorded lts-v2.12
  1. 02Pass
 Pass
8 Oct 23:28 tf-a-lts2.14-builder 242762 not recorded lts-v2.14
  1. 03Pass
 Pass
8 Oct 22:25 tf-a-builder 2565273 not recorded master built integration
  1. 02Pass
 Pass
8 Oct 21:29 tf-a-builder 2564431 not recorded master built integration
  1. 01Pass
 Pass
8 Oct 17:18 tf-a-lts2.10-builder 281088 55220/1 fix(fvp): absorb BUILD_CPUS_WITH_NO_FVP_MODEL and ENABLE_ERRATA_ALL cores lts-v2.10 built refs/changes/20/55220/1
  1. 02Pass
 Pass
8 Oct 08:52 tf-a-lts2.14-builder 242295 55214/2 refactor(cpus): rename Canyon to C2-Ultra lts-v2.14 built refs/changes/14/55214/2
  1. 02Pass
 Pass
8 Oct 08:11 tf-a-lts2.14-builder 241096 55214/1 refactor(cpus): rename Canyon to C2-Ultra lts-v2.14 built refs/changes/14/55214/1
  1. 01Pass
 Pass
8 Oct 07:08 tf-a-builder 2561861 55188/2 fix(fvp): remove GIC crash reporting integration built refs/changes/88/55188/2
  1. 02Pass
 Pass
8 Oct 06:41 tf-a-builder 2561229 54926/4 fix(psci): allow OS-initiated mode while other cores are off integration built refs/changes/26/54926/4
  1. 03Pass
 Pass
8 Oct 02:21 tf-a-lts2.8-builder 219784 not recorded lts-v2.8
  1. 03Pass
 Pass
8 Oct 01:34 tf-a-lts2.10-builder 280535 not recorded lts-v2.10
  1. 01Pass
 Pass
8 Oct 00:29 tf-a-lts2.12-builder 338369 not recorded lts-v2.12
  1. 01Pass
 Pass
7 Oct 23:33 tf-a-lts2.14-builder 240783 not recorded lts-v2.14
  1. 02Pass
 Pass
7 Oct 22:30 tf-a-builder 2560253 not recorded master built integration
  1. 03Pass
 Pass
7 Oct 15:10 tf-a-builder 2559490 52109/5 refactor(lfa): add fallback support integration built refs/changes/09/52109/5
  1. 03Pass
 Pass
7 Oct 12:48 tf-a-builder 2558838 54137/7 fix(cpufeat): correctly match the group 3 ID registers space integration built refs/changes/37/54137/7
  1. 03Pass
 Pass
7 Oct 12:10 tf-a-builder 2557799 55180/2 refactor(el3-spmc): remove excess overflow checks integration built refs/changes/80/55180/2
  1. 02Pass
 Pass
7 Oct 10:38 tf-a-builder 2557193 55179/1 fix(firme): fix attestation unmap error handling integration built refs/changes/79/55179/1
  1. 02Pass
 Pass
7 Oct 02:36 tf-a-lts2.8-builder 219509 not recorded lts-v2.8
  1. 01Pass
 Pass
7 Oct 01:15 tf-a-lts2.10-builder 279355 not recorded lts-v2.10
  1. 02Pass
 Pass
7 Oct 00:31 tf-a-lts2.12-builder 337902 not recorded lts-v2.12
  1. 02Pass
 Pass
6 Oct 23:27 tf-a-lts2.14-builder 239746 not recorded lts-v2.14
  1. 02Pass
 Pass
6 Oct 22:27 tf-a-builder 2550598 not recorded master built integration
  1. 02Pass
 Pass
6 Oct 21:00 tf-a-builder 2549867 55088/2 fix(psci): run the arch setup before pwr_domain_on_finish() integration built refs/changes/88/55088/2
  1. 01Pass
 Pass
6 Oct 20:54 tf-a-builder 2549676 54926/2 fix(psci): allow OS-initiated mode while other cores are off integration built refs/changes/26/54926/2
  1. 01Pass
 Pass
6 Oct 16:59 tf-a-builder 2547691 not recorded master
  1. 03Pass
 Pass
6 Oct 10:12 tf-a-builder 2547401 54944/2 refactor(cpus): separate helper files from cpu implementations integration built refs/changes/44/54944/2
  1. 01Pass
 Pass
6 Oct 02:19 tf-a-lts2.8-builder 218633 not recorded lts-v2.8
  1. 01Pass
 Pass
6 Oct 01:38 tf-a-lts2.10-builder 279024 not recorded lts-v2.10
  1. 03Pass
 Pass
6 Oct 00:20 tf-a-lts2.12-builder 336785 not recorded lts-v2.12
  1. 03Pass
 Pass
5 Oct 23:39 tf-a-lts2.14-builder 239150 not recorded lts-v2.14
  1. 02Pass
 Pass

Show the next 50

Fleet health

Health checks, not CI results. They never count towards any rate on this page.

0 of 20 health checks failed in the last 7 days.

All passed

Showing the latest 20 checks.

  1. Health check 3048754, Complete
  2. Health check 3048910, Complete
  3. Health check 3049075, Complete
  4. Health check 3049245, Complete
  5. Health check 3049354, Complete
  6. Health check 3049430, Complete
  7. Health check 3049600, Complete
  8. Health check 3049686, Complete
  9. Health check 3049766, Complete
  10. Health check 3049924, Complete
  11. Health check 3050115, Complete
  12. Health check 3050684, Complete
  13. Health check 3050847, Complete
  14. Health check 3051062, Complete
  15. Health check 3051309, Complete
  16. Health check 3051512, Complete
  17. Health check 3051678, Complete
  18. Health check 3051853, Complete
  19. Health check 3052025, Complete
  20. Health check 3052211, Complete

One tick per health check, oldest to newest. Each opens its job. Passed Failed Cancelled

Incidents

  1. Lab 17 Sep 2026 to 18 Sep 2026

    LAVA logger DNS failures